Let us consider the internal organization of a 64K*1 dynamic memory chip.

• The cells are arranged in the form of a square array.
• The higher order 8 bits of the 16 bits constitute the row address of the cell and the lower order 8 bits constitute the column address of a cell.
• The row and column addresses are multiplexed on eight pins
• During a Read or write operation the row address is applied first
• Row address is loaded in the Row address latch, RAS is applied. So the address is loaded into Row decoder
• Column address is loaded Column address latch, CAS is applied. So the address is loaded into Column decoder
• If the R/W’ control signal initiates a Read operation, output of the selected circuit is transferred to the data output DO
• To perform the write operation, the information at the data input DI is given to the column decoder
• Sense/write circuit is used to give the correct signal

Advantages

• High bit density
• Available chip range from 1k to 4k bits and even larger chips are being developed
• Low power dissipation

Disadvantage

• Slower speed of operation, refreshing required

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