1) Look aside design:

• In this case both the CPU and main memory are directly connected to the system bus.
• When a cache miss occurs, it results in data transfer between cache and main memory through the system bus making it unavailable for other I/O operations 

2) Look through design:

• In this the communication between CPU and cache is through a separate bus, which is isolated from the main system bus
• Hence the system bus is available for other units, such as I/O controllers to communicate with main memory
• In this the local bus linking main memory and cache is wider than the system bus. So the data transfer between cache and main memory is faster. Example: if system bus is 32 bits wide and if cache block size is 128 bits, a 128 bit data bus might be provided to link between cache and main memory
• The drawback of this design is that it takes more time for main memory to respond CPU when a cache miss occurs

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