• A technique used to increase the average memory access rate.
• Memory is divided into different modules and successive words are stored in different modules.
• If memory access requests are made for consecutive addresses, then the access will be made for different modules. Since parallel access to these modules is possible, the average rate of fetching words from the main memory can be increased
• In the fig. main memory is divided into 4 modules
• When the instruction fetch is issued by the processor, a memory access circuit creates 4 consecutive addresses and places them in 4 MARs
• A memory read command reads all the four modules simultaneously and retrieves 4 instructions. These are sent to the processor. Thus each Fetch instruction fetches 4 consecutive instructions

Combining Interleaving and cache

Interleaving and cache can be combined to reduce the speed mismatch between the cache memory and main memory

Example: Consider the time required for transferring a block of data from main memory to the cache when a read miss occurs Assumptions: Cache is 8 word block When a cache miss occurs, the block that contains desired word must be copied from the main memory into the cache.

Properties of H/W:

• It takes one clock cycle to send an address to the main memory
• The memory is build with DRAM chips that allow the first word to be accessed in 8 clock cycles, but subsequent words of the block are accessed in 4 clock cycles per word
• One clock cycle is needed to send one word to the cache

If a single memory is used, then the time needed to load the desired block into the cache is 1 + 8 + (7*4) +1 =38 cycle

1 to send an address to the main memory, 8 to read the first word, (7*4) to read next 7 word, 1 to load it to cache

Assume main memory is divided into 4 interleaved modules using interleaving technique. Let us see what is the difference?

• When the starting address of the block arrives at the memory all the four modules start accessing the required data
• After 8 clock cycles, each module has one word of data in MDR
• These words are transferred to the cache, one word at a time, during the next clock cycles ( so requires 4 clock cycles)
• During this time the next word in each module is accessed.(4 words are loaded in MDR)
• Then it takes another 4 cycles to transfer these words to cache
• Thus in total 8 words are loaded into the cache an entire block
• So the clock cycles required are
•   1(addess) + 8( four words read)  + 4 ( 4 words to cache and simultaneously next 4 words are read from memory) + 4 ( to transfer these 4 words to cache) = 17 cycles

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