Design of memory using Dynamic memory chips

• Dynamic memory chips are arranged in a 4 * 16 array.
• If the individual chips have 64K * 1 organization, then the storage capacity of the array is 256K words, each word is of 16 bits
• The control circuitry provides the multiplexed address, chip select , row and column address strobe signals (RAS and CAS) to the memory chip array
• Address lines, Data Lines, MFC, Read/Write line etc. are also present
Refresh circuitry is also present

Operation of the control circuitry for a memory read cycle

1. The cycle starts when the CPU activates the address, the Read/Write’ and the memory request lines
2. When the memory request signal becomes active, the access control block recognizes the request and it sets start signal to 1
3. The timing and control circuit sends a busy signal in order to prevent the access control box from accepting the new requests until the current cycle ends
4. The timing and control block then loads the row and column address into the memory chips by activating RAS and CAS. First it uses ROW/COLUMN’ line to select the row address(ADD15-8), followed by the column address(ADD7-0)
5. The decoder block decodes two most significant bits of the address and generates 4 chip select signals CS0-3
6. After obtaining the row and column parts of the address, the selected memory chips place the contents of the requested bit cells on their data outputs
7. This data is then transferred to the data lines of the memory bus through appropriate drivers
8. Now timing and control circuit send MFC signal to CPU indicating that the requested data is available on the memory bus
9. Finally the busy signal is deactivated so that the access control unit is now free to accept new requests

Control sequence for refresh operation

1. The refresh control block periodically generates refresh requests, causing the access control block to start a memory cycle in the normal way
2. The access control block arbitrates between memory access requests and refresh requests. If two requests are activated simultaneously, refresh requests are given priority in order to ensure that no information is lost
3. As soon as the refresh control block receives the refresh grant signal, it activates the refresh line
4. The address multiplexer selects the refresh counter as the source for the row address instead of ADD15-8 and the contents of the counter will be loaded into the row address latches of all the memory chips when the RAS signal is activated 
5. During this time, the R/W’ line may indicate a write operation. It is important to ensure that this does not inadvertently cause new information to be loaded into some of the cells that are being refreshed
6. At the end, refresh control block increments the refresh counter in preparation for the next refresh cycle

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