To execute the instructions, the CPU must generate the control signals in the proper sequence.
Two techniques to generate the control signals are
Hardwired control
Micro programmed control
HARDWIRED CONTROL
A decoder-encoder circuit generates the required control signals depending on the state of all inputs
Consider the sequence of control signals given in Table 2. In this seven non-overlapping time slots required to execute the instructions represented by this sequence. Each time slot must be at least long enough for the function specified in a particular step to be completed
Let us assume that all the time slots are equal in duration. So the control unit is designed based on the use of counter driven by a clock signal, CLK. Each state or count of this counter corresponds to one of the steps given in Table 2. Hence the required control signals are determined based on the following information
Contents of the Control counter
Contents of the Instruction Register
Contents of the control codes and other status flags
The status flag represents the state of various sections of the CPU and various control units connected to it. For example MFC
SEPERATION OF ENCODING AND DECODING UNITS
The step encoder provides a separate signal for each time slot in the control sequence. Similarly the output of instruction decoder consists of separate lines for each instruction.
When the Instruction is loaded into IR, one of the output lines INS1 to INSm is set to 1 and all other lines is set to 0.
All the input signals to encoder are combined to generate control signals such as Yin, PCout, ADD, AND etc.
The control signal Zin is generated by the logic function
Zin = T1 + T6.ADD +T5.BR+…
Z in is turned on during the time slot T1 for all instructions; during T6 for Add instruction and so on. Time T1 is common to all instructions because it occurs during the fetch phase