For transferring the data between the blocks of CPU, input and output gating must be provided Signals Ri(in) and Ri(out) control the input and output gates for register Ri When Ri(in) is set to 1, the data available on the common bus is loaded into Ri and when Ri(out) is set to 1, the contents of Ri are placed on the bus. When Ri(out) is set to 0, bus can be used for transferring data from other registers

• As an example consider a data transfer from register R0 to R1. To achieve this following sequence of operations are to be performed. 
• Set R0out to 1, which enables the output gate of register R0. This places the contents of R0 on the CPU bus.
• Set R1in to 1, which enables the input gate of register R1. This loads the content of R0 into register R1 from the CPU bus.

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