Each bus is connected to only one output and a number of inputs. Two registers A and B are provided, which can be loaded from either the input data bus or the register data bus.

Features:

• Three data transfers can take place at the same time.
• Components connected to each bus are less when compared to two bus architecture
• Hence Data Transfer is faster
• General purpose registers of the CPU are assumed to be implemented using a RAM unit.
• This RAM is different from RAM out side the CPU

EXECUTION OF A COMPLETE INSTRUCTION

Consider the instruction to add content of memory location NUM to register R0. Let the address NUM is given explicitly in the address field of instruction. Following table illustrates the control sequence for the execution of the instruction.
Following actions are performed to execute the instruction

1. Fetch the Instruction
2. Fetch the content of memory location pointed by the address field of the instruction
3. Perform addition
4. Load the result in R0
5. Contents of PC loaded into MAR and read request is sent to RAM. While waiting for MFC, PC is incremented. Meanwhile carry-in to ALU set to 1 and an Add operation is specified
6. The updated value from Z is sent back to PC, done without waiting for MFC
7. Wait for MFC. Word fetched from memory is loaded into IR----Fetch operation completes
8. Decoding of the instruction is done and control circuitry chooses the appropriate signals for the rest of the operation. Here the address field of IR, which contains the address NUM, is gated to MAR and a memory read operation is initiated.
9. Transfer the content of Ro to Y and wait for MFC
10. Now memory operand is available on register MDR. The addition operation is performed
11. The result is transferred to R0. -----end of execution phase
12. End signal indicates that this is the last step of current instruction and causes the new fetch cycle to be started at step 1

Control Sequence for the execution of the instruction

Table 2

Performing an Arithmetic or Logic Operation << Previous
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